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Abstract: Abstract
Managing thermal stress of high power silicon devices is critical in assuring long term
reliability. For LDMOS (Lateral Diffused Metal Oxide Semiconductor) power transistors,
thermal performance has traditionally been optimized using hard "AuSi" eutectic solder,
whereas, the flange is typically made of CuW, whose CTE is matched to silicon. This
research investigates the ... read morestress generated in silicon due to CTE mismatch as a result of
using a copper flange. Copper is a much more thermally conductive material, but it has a
CTE mismatch with the silicon die that can result in large stresses and potential
cracking of the die. A "ductile layer" technology has been developed to mitigate this
problem. This paper presents the finite element analysis of stresses and deformation of
eutectically soldered silicon chips to a copper flange incorporating the ductile layer
technology. In this study different geometric and material characteristics of the
ductile layer and the die are considered. The analysis shows that the stress in silicon
decreases by 20% and the ductile layer improves microcircuit packages reliability and
performance.
Thesis (M.S.)--Tufts University,
2011.
Submitted to the Dept. of Mechanical
Engineering.
Advisor: Michael
Zimmerman.
Committee: Anil Saigal, and Keith
Smith.
Keyword: Mechanical
Engineering.read less
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